1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to a method of saving information from the central processor of the computer.
2. Description of the Prior Art
The basic structure of a conventional computer system 10 is shown in FIG. 1. The heart of computer system 10 is a central processing unit (CPU) or processor 12 which is connected to several peripheral devices, including input/output (I/O) devices 14 (such as a display monitor and keyboard) for the user interface, a permanent memory device 16 (such as a hard disk or floppy diskette) for storing the computer's operating system and user programs, and a temporary memory device 18 (such as random access memory or RAM) that is used by processor 12 in carrying out program instructions. Processor 12 communicates with the peripheral devices by various means, including a bus 20 or a direct channel 22. Computer system 10 may have many additional components which are not shown, such as serial and parallel ports for connection to, e.g., modems or printers. Those skilled in the art will further appreciate that there are other components that might be used in conjunction with those shown in the block diagram of FIG. 1; for example, a display adapter connected to processor 12 might be used to control a video display monitor. Computer system 10 also includes firmware 24 whose primary purpose is to seek out and load an operating system from one of the peripherals (usually permanent memory device 16) whenever the computer is first turned on.
An illustrative embodiment of processor 12 is further shown in FIG. 2, which depicts the architecture for a PowerPC.TM. microprocessor manufactured by International Business Machines Corp. In this embodiment, processor 12 operates according to reduced instruction set computing (RISC) techniques, and is a single integrated circuit superscalar microprocessor. The system bus 20 is connected to a bus interface unit (BIU) 30 of processor 12. It is understood that bus 20, as well as various other connections described, include more than one line or wire, e.g., the bus could be a 32-bit bus. BIU 30 is connected an instruction cache 32 and a data cache 34. The output of instruction cache 32 is connected to a sequencer unit 36. In response to the particular instructions received from instruction cache 32, sequencer unit 36 outputs instructions to other execution circuitry of processor 12, including six execution units, namely, a branch unit 38, a fixed-point unit A (FXUA) 40, a fixed-point unit B (FXUB) 42, a complex fixed-point unit (CFXU) 44, a load/store unit (LSU) 46, and a floating-point unit (FPU) 48.
The inputs of FXUA 40, FXUB 42, CFXU 44 and LSU 46 also receive source operand information from general-purpose registers (GPRs) 50 and fixed-point rename buffers 52. The outputs of FXUA 40, FXUB 42, CFXU 44 and LSU 46 send destination operand information for storage at selected entries in fixed-point rename buffers 52. CFXU 44 further has an input and an output connected to special-purpose registers (SPRs) 54 for receiving and sending source operand information and destination operand information, respectively. An input of FPU 48 receives source operand information from floating-point registers (FPRs) 56 and floating-point rename buffers 58. The output of FPU 48 sends destination operand information to selected entries in floating-point rename buffers 58. Processor 12 may include other registers, such as configuration registers, memory management registers, exception handling registers, and miscellaneous registers, which are not shown. Processor 12 carries out program instructions (from a user application or the operating system) by routing the instructions and data to the appropriate execution units, buffers and registers, and by sending the resulting output to the memory device 18, or some output device such as a display console.
During operation of the computer system, it frequently becomes necessary to save the context of the registers, for example, when swapping out processes (multi-tasking), or handling exceptions. The manner in which the context is saved depends upon size of the registers, e.g., whether they are 32-bit registers, 64-bit registers operating in 64-bit mode, or 64-bit registers operating in 32-bit mode, because different instructions must be used to save the information depending upon the nature of the registers. Accordingly, separate sets of code are required to perform the context-saving routine for different register architectures. The operating system must examine the processor version register (PVR, one of the configuration registers mentioned above) in order to determine which set of codes are to be used throughout its operation. At a given processor architecture version, whenever a new processor is available, the operating system must be modified to recognize the new PVR value since it may not be known previously. It would, therefore, be desirable to devise a method of saving a processor's register context which can be used for any processor version, present or future, of a given processor architecture version. Furthermore, when the processor architecture is changed to a newer version to include larger register size, it is desirable that the method could be easily expanded to cover the larger size registers with newly defined instructions which can handle them.